Code Generation and Data Layout Transformation Techniques for Processing-in-Memory 


Vol. 50,  No. 8, pp. 639-645, Aug.  2023
10.5626/JOK.2023.50.8.639


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  Abstract

Processing-in-Memory (PIM) capitalizes on internal parallelism and bandwidth within memory systems, thereby achieving superior performance to CPUs or GPUs in memory-intensive operations. Although many PIM architectures were proposed, the compiler issues for PIM are not currently well-studied. To generate efficient program codes for PIM devices, the PIM compiler must optimize operation schedules and data layouts. Additionally, the register reuse of PIM processing units must be maximized to reduce data movement traffic between host and PIM devices. We propose a PIM compiler, which can support various PIM architectures. It achieves up to 2.49 times performance improvement in GEMV operations through register reuse optimization.


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  Cite this article

[IEEE Style]

H. Lee, G. Kim, D. Shin, "Code Generation and Data Layout Transformation Techniques for Processing-in-Memory," Journal of KIISE, JOK, vol. 50, no. 8, pp. 639-645, 2023. DOI: 10.5626/JOK.2023.50.8.639.


[ACM Style]

Hayun Lee, Gyungmo Kim, and Dongkun Shin. 2023. Code Generation and Data Layout Transformation Techniques for Processing-in-Memory. Journal of KIISE, JOK, 50, 8, (2023), 639-645. DOI: 10.5626/JOK.2023.50.8.639.


[KCI Style]

이하윤, 김경모, 신동군, "Processing-in-Memory를 위한 코드 생성 및 데이터 레이아웃 변형 기법," 한국정보과학회 논문지, 제50권, 제8호, 639~645쪽, 2023. DOI: 10.5626/JOK.2023.50.8.639.


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