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Design and Implementation of a Tactical-datalink Unit for Interfacing and Forwarding(TUF) to Interlock and Forward MIDS JTRS
Sangtae Lee, Jongseo Kim, Taegwon Kim, Youngseung Kim, Seungbae Jee, Jaeyoung Cheon, MinGyu Jung
http://doi.org/10.5626/JOK.2024.51.3.252
The MIDS LVT terminal is changed to MIDS JTRS terminals with improved crypto modernization, enhanced throughput and frequency remapping functions due to encryption keys and bandwidth limitations. The Korean military is carrying out various performance improvement projects for the Link-16 network equipped with a MIDS JTRS terminal. In this paper, a tactical datalink unit for interfacing and forwarding(TUF) was designed and implemented to interlock and forward tactical information to the existing C2 host system (MCRC, KTMO, etc.) using MIDS JTRS terminal.
The TUF had improved scalability and maintainability through a server-client structure design that could remotely control and manage MIDS JTRS terminal interlocking and forwarding in consideration of the network operating environment. The TUF consisted of interlocking and forwarding, a basic C2 (command & control) host, and a monitoring tool. The TUF was verified through linkage with previously verified overseas tools. The TUF secured technical know-how for MIDS JTRS terminal integration by achieving the purpose of interlocking and forwarding through domestic technology development, away from the existing method of interlocking and forwarding through overseas tools. The existing weapon system without MIDS JTRS terminal linkage function could join the Link-16 network to enhance military operational operability and survivability.
Design and Implementation of Framework Based Emulator Considering Expansion of MIDS LVT Platform
Sangtae Lee, Jongseo Kim, Sounghyouk Wi, Taegwon Lee, Seungbae Jee, Seungchan Lee
http://doi.org/10.5626/JOK.2021.48.1.61
MIDS LVT is communication equipment mounted with Link-16-based weapon systems to provide the Link-16 operating environment between weapon systems. Currently, the military operates the MIDS LVT BU1, but it will be changed to the BU2 and JTRS according to the performance improvement. The communication interface, message data format, and message composition of the MIDS LVT are different depending on the platform family (BU1/BU2/JTRS) and type (A,D,J). In this paper, we propose a framework based emulator design and implementation method that considers the MIDS LVT platform extension to improve these problems. In consideration of the quality attributes of the sw architecture, we designed a common based framework for modifiability, reusability, and extensibility. The MIDS LVT emulator comprises the MIDS LVT emulator processing, link interface processing, and monitoring tool. The MIDS LVT emulator was implemented by deriving and improving functions through the analysis of the functions of the previously developed overseas tools. Through the development of the MIDS LVT emulator, it can be used to develop and verify the developed Link-16 host system.
A Function-characteristic Aware Thread-mapping Strategy for an SEDA-based Message Processor in Multi-core Environments
Heeeun Kang, Sungyong Park, Younjeong Lee, Seungbae Jee
A message processor is server software that receives various message formats from clients, creates the corresponding threads to process them, and lastly delivers the results to the destination. Considering that each function of an SEDA-based message processor has its own characteristics such as CPU-bound or IO-bound, this paper proposes a thread-mapping strategy called "FC-TM" (function-characteristic aware thread mapping) that schedules the threads to the cores based on the function characteristics in multi-core environments. This paper assumes that message-processor functions are static in the sense that they are pre-defined when the message processor is built; therefore, we profile each function in advance and map each thread to a core using the information in order to maximize the throughput. The benchmarking results show that the throughput increased by up to a maximum of 72 % compared with the previous studies when the ratio of the IO-bound functions to the CPU-bound functions exceeds a certain percentage.
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