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Overcoming a Zone Reclaiming Overhead with Partial-Zone Reclaiming
Inho Song, Wonjin Lee, Jaedong Lee, Seehwan Yoo, Jongmoo Choi
http://doi.org/10.5626/JOK.2024.51.2.115
Solid State Drive (SSD) suffers unpredictable IO latency and space amplification due to the traditional block interface. Zoned Namespace, which is a more flash friendly interface, replaced the block interface bringing reliable IO latency and increasing both the capacity and lifespan of SSDs. The benefit of the zone interface is not free. A Zoned Namespace (ZNS) SSD delegates the garbage collection and data placement responsibility to the host, which requires host-level garbage collection called "zone reclaiming". At the same time, ZNS SSD exposes a larger zone to the host to exploit the device parallelism. The increased number of blocks to a zone gives high parallelism; however, the overhead of the zone reclaiming process becomes high with the increased size of the zone. Eventually, the host neither expects predictable latency nor optimal performance due to the background process. This paper tackles the overhead of the zone reclaiming process by introducing "Partial Zone Reclaiming" method. Partial zone reclaiming delays the ongoing reclaiming process and handles the host request that is on the fly. In our experiment, partial zone reclaiming not only improved the host request latency by up to 8% on average, but also reduced zone reclaiming time by up to 41%.
ESP: Improving Performance and Lifetime of High-Capacity 3D Flash Storage Using an Erase-Free Subpage Programming Technique
http://doi.org/10.5626/JOK.2023.50.1.1
Recent high-capacity 3D NAND flash devices have large page sizes. Although large pages are useful in increasing flash capacity, they can degrade both the performance and lifetime of flash storage systems when small writes are dominant. We propose a new NAND programming scheme, called erase-free sub-page programming (ESP), which allows the same page to be programmed multiple times for small writes without the intervention of the erase operation. By avoiding internal fragmentation, the ESP scheme reduces the overhead of garbage collection for large-page NAND storage. Based on the proposed ESP scheme with an adaptive retention management technique, we implemented an ESP-aware FTL(subFTL) and performed comprehensive evaluations using various benchmarks and workloads. The experimental results showed that an ESP-aware FTL could improve the IOPS and lifetime by up to 74% and 177%, respectively.
MQSim-E: Design and Implementation of an NVMe SSD Simulator for Enterprise SSDs
Duwon Hong, Dusol Lee, Jihong Kim
http://doi.org/10.5626/JOK.2022.49.4.271
In the study of storage systems such as SSD, a simulator that accurately mimic the operation of SW/HW inside the system plays an important role. In this paper, MQSim, which is widely used in research on NVMe SSDs, was shown to be inappropriate for the development of enterprise-SSD, and we propose an MQSim-E simulator that supports optimized techniques adopted in enterprise-SSD. MQSim-E fully utilizes the parallelism of flash memory and minimizes the performance overhead of garbage collection, improving IOPS, which is an important design goal for enterprise-SSDs, by up to 210% and reducing tail latency by up to 16,000% compared to the existing simulator (MQSim) to accurately reflect the characteristics of commercial enterprise SSDs.
New Flash Commands for Building Flash Storage Systems with Plausible Deniability
Geonhee Cho, Myungsuk Kim, Jihong Kim
http://doi.org/10.5626/JOK.2022.49.2.120
Traditional encryption cannot defend against coercive attackers who compel the user to hand over decryption keys as it cannot hide the existence of the ciphertext. To solve this problem, there have been studies on a deniable storage solution that applies plausible deniability, a characteristic that allows the user to deny the existence of sensitive data, to a storage device. The hidden volume mechanism is being used in various deniable storage solutions due to its relatively low-performance overhead compared to other mechanisms, and has recently evolved to defend against multiple-snapshot attacks. However, the existing hidden volume mechanism fundamentally requires a dummy random data pool to hide the ciphertext. Due to the existence of dummy random data stored in the storage device, the plausible deniability characteristic is exposed, which can reveal the intention to hide the data. This study proposes a flash chip-level access control command set that simultaneously supports data sanitization and plausible deniability, and using this, we propose a hidden volume-based deniable storage solution that supports plausible deniability characteristics without dummy random data.
An Efficient SLC-buffer Management Scheme for TLC NAND Flash-based Storage
Kirock Kwon, Dong Hyun Kang, Young Ik Eom
http://doi.org/10.5626/JOK.2018.45.7.611
In recent years, almost all consumer devices have adopted NAND flash storage as their main storage, and their performance and capacity requirements are getting higher. To meet these requirements, many researchers have focused on combined SLC-TLC storage consisting of high-speed SLC and high-density TLC. In this paper, we redesign the internal structure of the combined SLC-TLC storage to efficiently manage the SLC region inside the storage and propose a scheme that improves the performance of the storage by employing the I/O characteristics of file system journaling. We implemented our scheme on the real storage platform, the OpenSSD jasmine board, and compared it with the conventional techniques. Our evaluation results show that our technique improves the storage performance by up to 65%, compared with the conventional techniques.
A Cross Layer Optimization Technique for Improving Performance of MLC NAND Flash-Based Storages
Jisung Park, Sungjin Lee, Jihong Kim
http://doi.org/10.5626/JOK.2017.44.11.1130
The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.
Dual Write Buffer Algorithm for Improving Performance and Lifetime of SSDs
Se Jun Han, Dong Hyun Kang, Young Ik Eom
In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.
Improving the Lifetime of NAND Flash-based Storages by Min-hash Assisted Delta Compression Engine
Hyoukjun Kwon, Dohyun Kim, Jisung Park, Jihong Kim
In this paper, we propose the Min-hash Assisted Delta-compression Engine(MADE) to improve the lifetime of NAND flash-based storages at the device level. MADE effectively reduces the write traffic to NAND flash through the use of a novel delta compression scheme. The delta compression performance was optimized by introducing min-hash based LSH(Locality Sensitive Hash) and efficiently combining it with our delta compression method. We also developed a delta encoding technique that has functionality equivalent to deduplication and lossless compression. The results of our experiment show that MADE reduces the amount of data written on NAND flash by up to 90%, which is better than a simple combination of deduplication and lossless compression schemes by 12% on average.
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