Search : [ keyword: NAND flash memory ] (4)

ESP: Improving Performance and Lifetime of High-Capacity 3D Flash Storage Using an Erase-Free Subpage Programming Technique

Myungsuk Kim

http://doi.org/10.5626/JOK.2023.50.1.1

Recent high-capacity 3D NAND flash devices have large page sizes. Although large pages are useful in increasing flash capacity, they can degrade both the performance and lifetime of flash storage systems when small writes are dominant. We propose a new NAND programming scheme, called erase-free sub-page programming (ESP), which allows the same page to be programmed multiple times for small writes without the intervention of the erase operation. By avoiding internal fragmentation, the ESP scheme reduces the overhead of garbage collection for large-page NAND storage. Based on the proposed ESP scheme with an adaptive retention management technique, we implemented an ESP-aware FTL(subFTL) and performed comprehensive evaluations using various benchmarks and workloads. The experimental results showed that an ESP-aware FTL could improve the IOPS and lifetime by up to 74% and 177%, respectively.

Improving Performance of Flash Storage Using Restricted Copyback

Duwon Hong, Seulgi Shin, Jihong Kim

http://doi.org/10.5626/JOK.2019.46.8.726

In case of modern flash-based SSDs, the performance overhead of internal data migrations is dominated by the data transfer time and not by the flash program time as in old SSDs. In order to mitigate the performance impact of data migrations, we propose rcopyback, a restricted version of copyback. Rcopyback works in a manner similar to the original copyback except that only n consecutive copybacks are allowed. By limiting the number of successive copybacks, the version guarantees internal migration of data using rcopyback without any reliability problem. In order to take a full advantage of rcopyback, we developed a rcopyback-aware FTL, rcFTL, which intelligently decides whether rcopyback should be used or not by exploiting varying host workloads. Our evaluation results show that rcFTL can improve the overall I/O throughput by 54% on average over an existing FTL which does not use copybacks.

A Cross Layer Optimization Technique for Improving Performance of MLC NAND Flash-Based Storages

Jisung Park, Sungjin Lee, Jihong Kim

http://doi.org/10.5626/JOK.2017.44.11.1130

The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.

Dual Write Buffer Algorithm for Improving Performance and Lifetime of SSDs

Se Jun Han, Dong Hyun Kang, Young Ik Eom

http://doi.org/

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.


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