Search : [ keyword: Processing-in-Memory (PIM) ] (2)

Analysis of GEMV Kernel Computations by Address Mapping Approaches Based on GPU and PIM Architectures

Jiwon Shin, Gunjae Koo

http://doi.org/10.5626/JOK.2025.52.6.469

Processing-in-Memory (PIM) is an architectural approach that can overcome bandwidth limitations between host processors and off-chip memory. PIM can improve data computation performance by exploiting high internal bandwidth and parallel computations within a memory module. Therefore, it is expected that PIMs can be paired with high-performance processors such as GPUs to achieve overall performance improvements. However, due to differences in memory address mapping schemes between PIM and GPU architectures, applying PIM's address mapping method directly to GPUs may result in a decrease in overall performance. In this paper, we analyze the performance impact of PIM's address mapping schemes on GPU using memory-intensive general matrix-vector product (GEMV) kernels. Our evaluation results exhibit that PIM’s address mapping schemes degrade performance and memory bandwidth on GPUs, indicating that differences in mapping schemes could potentially cause performance degradation in GPU-PIM architectures.

Code Generation and Data Layout Transformation Techniques for Processing-in-Memory

Hayun Lee, Gyungmo Kim, Dongkun Shin

http://doi.org/10.5626/JOK.2023.50.8.639

Processing-in-Memory (PIM) capitalizes on internal parallelism and bandwidth within memory systems, thereby achieving superior performance to CPUs or GPUs in memory-intensive operations. Although many PIM architectures were proposed, the compiler issues for PIM are not currently well-studied. To generate efficient program codes for PIM devices, the PIM compiler must optimize operation schedules and data layouts. Additionally, the register reuse of PIM processing units must be maximized to reduce data movement traffic between host and PIM devices. We propose a PIM compiler, which can support various PIM architectures. It achieves up to 2.49 times performance improvement in GEMV operations through register reuse optimization.


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